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5.0 kv rms, 5-channel digital isolators data sheet adum250n / adum251n / adum252n rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2016 analog devices, inc. all rights reserved. technical support www.analog.com features high common-mode transient immunity: 100 kv/s high robustness to radiated and conducted noise low propagation delay 13 ns maximum for 5 v operation 15 ns maximum for 1.8 v operation 150 mbps maximum guaranteed data rate safety and regulatory approvals (pending) ul recognition: 5000 v rms for 1 minute per ul 1577 csa component acceptance notice 5a vde certificate of conformity din v vde v 0884-10 (vde v 0884-10):2006-12 v iorm = 849 v peak cqc certification per gb4943.1-2011 low dynamic power consumption 1.8 v to 5 v level translation high temperature operation: 125c fail-safe high or low options 16-lead, rohs compliant, wide-body soic_ic package applications general-purpose multichannel isolation serial peripheral interface (spi)/data converter isolation industrial field bus isolation general description the adum250n / adum251n / adum252n 1 are 5-channel digital isolators based on analog devices, inc., i coupler? technology. combining high sp eed, complementary metal-oxide semiconductor (cmos) and monolithic air core transformer technology, these isolation components provide outstanding performance characteristics superior to alternatives such as optocoupler devices and other integrated couplers. the maximum propagation delay is 13 ns with a pulse width distortion of less than 4.5 ns at 5 v operation. channel to channel matching of propagation delay is tight at 4.0 ns maximum. the adum250n / adum251n / adum252n data channels are independent and are available in a variety of configurations with a withstand voltage rating of 5.0 kv rms (see the ordering guide). the devices operate with the supply voltage on either side ranging from 1.7 v to 5.5 v, providing compatibility with lower voltage systems as well as enabling voltage translation functionality across the isolation barrier. functional block diagrams figure 1. adum250n functional block diagram figure 2. adum251n functional block diagram figure 3. adum252n functional block diagram unlike other optocoupler alternatives, dc correctness is ensured in the absence of input logic transitions. two different fail-safe options are available by which the outputs transition to a predeter- mined state when the input power supply is not applied. 1 protected by u.s. patents 5,952,849; 6,873,065; 6, 903,578; and 7,075,329. other patents are pending. encode decode encode decode encode decode encode decode encode decode v dd1 v ia v ib v ic v id v ie nic v oa v ob v oc v od v oe nic gnd 1 v dd2 adum250n gnd 2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 14997-001 encode decode encode decode encode decode encode decode v dd1 v ia v ib v ic v id v oe nic v oa v ob v oc v od v ie nic gnd 1 v dd2 adum251n gnd 2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 decode encode 14997-002 encode decode encode decode encode decode v dd1 v ia v ib v ic v od v oe nic v oa v ob v oc v id v ie nic gnd 1 v dd2 adum252n gnd 2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 decode encode decode encode 14997-003
adum250n/a dum251n/adum252n data sheet rev. 0 | page 2 of 22 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general descript ion ......................................................................... 1 functional block diagrams ............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical cha racteristics 5 v operation ................................ 3 electrical characteristics 3.3 v operation ............................ 5 electrical characteristics 2.5 v operation ............................ 7 electrical characteristics 1.8 v operation ............................ 9 insulation and safety related specifications .......................... 11 package characteristics ............................................................. 11 regu latory information ............................................................. 11 din v vde v 0884 - 10 (vde v 0884 - 10) insulation characteristics ............................................................................ 12 recommended operating conditions .................................... 12 absolute maximum ratings ......................................................... 13 esd caution ................................................................................ 13 pin configurations and function descriptions ......................... 14 typical performance characteristics ........................................... 17 theory of operation ...................................................................... 19 applications information .............................................................. 20 pcb layout ................................................................................. 20 propagation delay related parameters ................................... 20 jitter measurement ..................................................................... 20 insulation lifetime ..................................................................... 20 outline dimensions ....................................................................... 22 ordering guide .......................................................................... 22 revision history 12/ 20 16 revision 0 : initial version
data sheet adum250n/adum251n/adum252n rev. 0 | page 3 of 22 specifications electrical character istics 5 v operation all typical specifications are at t a = 25c, v dd1 = v dd2 = 5 v. m inimum/maximum specifications apply over the entire recommended operation range of 4.5 v v dd1 5.5 v, 4.5 v v dd2 5.5 v, and ? 40c t a + 125c , unless otherwise noted. switching specifications are tested with c l = 15 pf and cmos signal levels, unless otherwise noted. supply currents are specified with 50% duty cycle signals. table 1 . parameter symbol min typ max unit test conditions/comments switching specifications pulse width pw 6.6 ns within pulse width distortion (pwd) limit data rate 1 150 mbps within pwd limit propagation delay t phl , t plh 4.8 7.2 13 ns 50% input to 50% output pulse width distortion pwd 0.5 4.5 ns |t plh ? t phl | change vs. temperature 1.5 ps/c propagation delay skew t psk 6.1 ns between any two units at the same temperature, voltage, and load channel matching codirectional t pskcd 0.5 4.0 ns opposing direction t pskod 0.5 4.5 ns jitter 490 ps p -p see the jitter measurement section 70 ps rms see the jitter measurement section dc specifications input threshold voltage logic high v ih 0.7 v ddx v logic low v il 0.3 v ddx v output voltage logic high v oh v ddx ? 0.1 v ddx v i ox 2 = ?20 a, v ix = v ixh 3 v ddx ? 0.4 v ddx ? 0.2 v i ox 2 = ?4 ma, v ix = v ixh 3 logic low v ol 0.0 0.1 v i ox 2 = 20 a, v ix = v ixl 4 0.2 0.4 v i ox 2 = 4 ma, v ix = v ixl 4 input current per channel i i ?10 +0.01 +10 a 0 v v ix v ddx quiescent supply current adum 2 50n i dd1 (q) 2.54 3.7 0 ma v i 5 = 0 ( n0 ), 1 ( n 1) 6 i dd2 (q) 3.34 4.56 ma v i 5 = 0 ( n 0), 1 ( n 1) 6 i dd1 (q) 16.8 27.5 ma v i 5 = 1 ( n 0), 0 (n 1) 6 i dd2 (q) 3.57 4.9 0 ma v i 5 = 1 (n0), 0 (n 1) 6 adum 2 51n i dd1 (q) 2.79 4.09 ma v i 5 = 0 (n0), 1 (n1) 6 i dd2 (q) 3.20 4.22 ma v i 5 = 0 (n0), 1 (n1) 6 i dd1 (q) 14.2 23 ma v i 5 = 1 (n0), 0 (n1) 6 i dd2 (q) 7.08 11.1 ma v i 5 = 1 (n0), 0 (n1) 6 adum 2 52n i dd1 (q) 2.91 4.11 ma v i 5 = 0 (n0), 1 (n1) 6 i dd2 (q) 2.95 4.15 ma v i 5 = 0 (n0), 1 (n1) 6 i dd1 (q) 11.1 19.5 ma v i 5 = 1 (n0), 0 (n1) 6 i dd2 (q) 10.5 16.7 ma v i 5 = 1 (n0), 0 (n1) 6 dynamic supply current inputs switching, 50% duty cycle dynamic input i ddi (d) 0.01 ma/mbps dynamic output i ddo (d) 0.02 ma/mbps
adum250n/a dum251n/adum252n data sheet rev. 0 | page 4 of 22 parameter symbol min typ max unit test conditions/comments undervoltage lockout uvlo positive v ddx threshold v ddxuv+ 1.6 v negative v ddx threshold v ddxuv? 1.5 v v ddx hysteresis v ddxuvh 0.1 v ac specifications output rise/fall time t r /t f 2.5 ns 10% to 90% common - mode transient immunity 7 |cm h | 75 100 kv/s v ix = v ddx , v cm = 1000 v, transient magnitude = 800 v |cm l | 75 100 kv/s v ix = 0 v, v cm = 1000 v, transient magnitude = 800 v 1 150 mbps is the highest data rate that can be guaranteed, although higher data rates are possible. 2 i ox is t he cha nnel x output current, where x = a, b, c, d , or e . 3 v ixh is the input side logic high. 4 v ixl is the input side logic low. 5 v i is the voltage input. 6 n 0 refers to the adum 2 50n0 / adum 2 51n0 / adum 2 52n0 models. n 1 refers to the adum 2 50n1 / adum 2 51n1 / adum 2 52n1 models . see the ordering guide section. 7 |cm h | is the maximum common - mode voltage slew rate that can be sustained while maintaining the voltage output (v o ) > 0.8 v ddx . |cm l | is the maximum common - mode voltage slew rate that can be sustained while maintaining the output voltage ( v o ) > 0.8 v. the common - mode voltage slew rates apply to both rising and falling common - mode voltage edges. table 2 . total supply current vs. data throughput 1 mbps 25 mbps 100 mbps parameter symbol min typ max min typ max min typ max unit supply current adum 2 50n supply current side 1 i dd1 9. 63 14.6 10. 9 17.1 1 6.0 24.0 ma supply current side 2 i dd2 3. 61 5.61 5. 36 8.5 0 1 1.1 19.0 ma adum 2 51n supply current side 1 i dd1 8.51 13.7 9.85 16.1 15.0 23.3 ma supply current side 2 i dd2 5.28 8.95 6.89 11.5 12.3 20.0 ma adum 2 52n supply current side 1 i dd1 7.08 11.6 8.56 13.9 13.7 20.4 ma supply current side 2 i dd2 6.83 10.5 8.35 12.8 13.4 20.6 ma
data sheet adum250n/adum251n/adum252n rev. 0 | page 5 of 22 electrical character istics 3.3 v operation all typical specifications are at t a = 25c, v dd1 = v dd2 = 3.3 v. minimum/maximum specifications apply over the entire recommended operation range: 3.0 v v dd1 3.6 v, 3.0 v v dd2 3.6 v, and ? 40c t a + 125 c, unless otherwise noted. switching specifications are tested with c l = 15 pf and cmos signal levels, unless otherwise noted. supply currents are specified with 50% duty cycle signals. table 3 . parameter symbol min typ max unit t est conditions/comments switching specifications pulse width pw 6.6 ns within pwd limit data rate 1 150 mbps within pwd limit propagation delay t phl , t plh 4.8 6.8 14 ns 50% input to 50% output pulse width distortion pwd 0.7 4.5 ns |t plh ? t phl | change vs. temperature 1.5 ps/c propagation delay skew t psk 7.5 ns between any two units at the same temperature, voltage, and load channel matching codirectional t pskcd 0.7 4.0 ns opposing direction t pskod 0.7 4.5 ns jitter 580 ps p -p see the jitter measurement section 120 ps rms see the jitter measurement section dc specifications input threshold voltage logic high v ih 0.7 v ddx v logic low v il 0.3 v ddx v output voltage logic high v oh v ddx ? 0.1 v ddx v i ox 2 = ?20 a, v ix = v ixh 3 v ddx ? 0.4 v ddx ? 0.2 v i ox 2 = ?2 ma, v ix = v ixh 3 logic low v ol 0.0 0.1 v i ox 2 = 20 a, v ix = v ixl 4 0.2 0.4 v i ox 2 = 2 ma, v ix = v ixl 4 input current per channel i i ?10 +0.01 +10 a 0 v v ix v ddx quiescent supply current adum 2 50n i dd1 (q) 2 .36 3.52 ma v i 5 = 0 (n0), 1 (n1) 6 i dd2 (q) 3.2 0 4.42 ma v i 5 = 0 (n0), 1 (n1) 6 i dd1 (q) 1 6.5 27.2 ma v i 5 = 1 (n0), 0 (n1) 6 i dd2 (q) 3.43 4.76 ma v i 5 = 1 (n0), 0 (n1) 6 adum 2 51n i dd1 (q) 2.61 3.91 ma v i 5 = 0 (n0), 1 (n1) 6 i dd2 (q) 3.05 4.07 ma v i 5 = 0 (n0), 1 (n1) 6 i dd1 (q) 14.0 22.8 ma v i 5 = 1 (n0), 0 (n1) 6 i dd2 (q) 6.91 10.9 ma v i 5 = 1 (n0), 0 (n1) 6 adum 2 52n i dd1 (q) 2.74 3.94 ma v i 5 = 0 (n0), 1 (n1) 6 i dd2 (q) 2.79 3.99 ma v i 5 = 0 (n0), 1 (n1) 6 i dd1 (q) 10.9 19.3 ma v i 5 = 1 (n0), 0 (n1) 6 i dd2 (q) 10.3 16.5 ma v i 5 = 1 (n0), 0 (n1) 6 dynamic supply current inputs switching, 50% duty cycle dynamic input i ddi (d) 0.01 ma/mbps dynamic output i ddo (d) 0.01 ma/mbps undervoltage lockout uvlo positive v ddx threshold v ddxuv+ 1.6 v negative v ddx threshold v ddxuv? 1.5 v v ddx hysteresis v ddxuvh 0.1 v
adum250n/a dum251n/adum252n data sheet rev. 0 | page 6 of 22 parameter symbol min typ max unit t est conditions/comments ac specifications output rise/fall time t r /t f 2.5 ns 10% to 90% common - mode transient immunity 7 |cm h | 75 100 kv/s v ix = v ddx , v cm = 1000 v, transient magnitude = 800 v |cm l | 75 100 kv/s v ix = 0 v, v cm = 1000 v, transient magnitude = 800 v 1 150 mbps is the highest data rate that can be guaranteed, although higher data rates are possible. 2 i ox is t he channel x outp ut curren t , where x = a, b, c, d , or e . 3 v ixh is the input side logic high. 4 v ixl is the input side logic low. 5 v i is the voltage input. 6 n 0 refers to the adum 2 50n0 / adum 2 51n0 / adum 2 52n0 models. n 1 refers to the adum 2 50n1 / adum 2 51n1 / adum 2 52n1 models . see the ordering guide section. 7 |cm h | is the maximum common - mode voltage slew rate that can be sustained while maintaining the voltage output (v o ) > 0.8 v ddx . |cm l | is the maximum common - mode voltage slew rate that can be sustained while maintaining v o > 0.8 v. the common - mode voltage slew rates apply to both rising and falling common - mode voltag e edges. table 4 . total supply current vs. data throughput 1 mbps 25 mbps 100 mbps parameter symbol min typ max min typ max min typ max unit supply current adum 2 50n supply current side 1 i dd1 9.36 14.3 10.4 16. 6 14.6 22.6 ma supply current side 2 i dd2 3.45 5.45 5.03 8.23 10.2 18.1 ma adum 2 51n supply current side 1 i dd1 8.26 13.5 9.41 15.7 13.9 22.2 ma supply current side 2 i dd2 5.09 8.76 6.55 11.2 11.4 19.1 ma adum 2 52n supply current side 1 i dd1 6.84 11.3 8.12 13.5 12.7 19.4 ma supply current side 2 i dd2 6.60 10.3 7.94 12.4 12.6 19.8 ma
data sheet adum250n/adum251n/adum252n rev. 0 | page 7 of 22 electrical character istics 2.5 v operation all typical specifications are at t a = 25c, v dd1 = v dd2 = 2.5 v. minimum/maximum specifications apply over the entire recommended operation range: 2.25 v v dd1 2.75 v, 2.25 v v dd2 2.75 v, ? 40c t a + 125c, unless otherwise noted. switching specifications are tested with c l = 15 pf and cmos signal levels, unless otherwise noted. supply curr ents are specified with 50% duty cycle signals. table 5 . parameter symbol min typ max unit test conditions/comments switching specifications pulse width pw 6.6 ns within pwd limit data rate 1 150 mbps within pwd limit propagation delay t phl , t plh 5.0 7.0 14 ns 50% input to 50% output pulse width distortion pwd 0.7 5.0 ns |t plh ? t phl | change vs. temperature 1.5 ps/c propagation delay skew t psk 6.8 ns between any two units at the same temperature, voltage, load channel matching codirectional t pskcd 0.7 5.0 ns opposing direction t pskod 0.7 5.0 ns jitter 800 ps p -p see the jitter measurement section 190 ps rms see the jitter measurement section dc specifications input threshold voltage logic high v ih 0.7 v ddx v logic low v il 0.3 v ddx v output voltage logic high v oh v ddx ? 0.1 v ddx v i ox 2 = ?20 a, v ix = v ixh 3 v ddx ? 0.4 v ddx ? 0.2 v i ox 2 = ?2 ma, v ix = v ixh 3 logic low v ol 0.0 0.1 v i ox 2 = 20 a, v ix = v ixl 4 0.2 0.4 v i ox 2 = 2 ma, v ix = v ixl 4 input cu rrent per channel i i ?10 +0.01 +10 a 0 v v ix v ddx quiescent supply current adum 2 50n i dd1 (q) 2. 28 3.44 ma v i 5 = 0 (n0), 1 (n1) 6 i dd2 (q) 3.13 4.35 ma v i 5 = 0 (n0), 1 (n1) 6 i dd1 (q) 16.4 27.1 ma v i 5 = 1 (n0), 0 (n1) 6 i dd2 (q) 3. 34 4.67 ma v i 5 = 1 (n0), 0 (n1) 6 adum 2 51n i dd1 (q) 2.52 3.82 ma v i 5 = 0 (n0), 1 (n1) 6 i dd2 (q) 2.97 3.99 ma v i 5 = 0 (n0), 1 (n1) 6 i dd1 (q) 13.9 22.7 ma v i 5 = 1 (n0), 0 (n1) 6 i dd2 (q) 6.83 10.8 ma v i 5 = 1 (n0), 0 (n1) 6 adum 2 52n i dd1 (q) 2.66 3.86 ma v i 5 = 0 (n0), 1 (n1) 6 i dd2 (q) 2.71 3.91 ma v i 5 = 0 (n0), 1 (n1) 6 i dd1 (q) 10.8 19.2 ma v i 5 = 1 (n0), 0 (n1) 6 i dd2 (q) 10.2 16.4 ma v i 5 = 1 (n0), 0 (n1) 6 dynamic supply current inputs switching, 50% duty cycle dynamic input i ddi (d) 0.01 ma/mbps dynamic output i ddo (d) 0.01 ma/mbps undervoltage lockout positive v ddx threshold v ddxuv+ 1.6 v negative v ddx threshold v ddxuv? 1.5 v v ddx hysteresis v ddxuvh 0.1 v
adum250n/a dum251n/adum252n data sheet rev. 0 | page 8 of 22 parameter symbol min typ max unit test conditions/comments ac specifications output rise/fall time t r /t f 2.5 ns 10% to 90% common - mode transient immunity 7 |cm h | 75 100 kv/s v ix = v ddx , v cm = 1000 v, transient magnitude = 800 v |cm l | 75 100 kv/s v ix = 0 v, v cm = 1000 v, transient magnitude = 800 v 1 150 mbps is the highest data rate that can be guaranteed, although higher data rates are possible. 2 i ox is t he channe l x o utput current , where x = a, b, c, d , or e . 3 v ixh is the input side logic high. 4 v ixl is the input side logic low. 5 v i i s the voltage input. 6 n 0 refers to the adum 2 50n0 / adum 2 51n0 / adum 2 52n0 models. n 1 refers to the adum 2 50n1 / adum 2 51n1 / adum 2 52n1 models . see the ordering guide section. 7 |cm h | is the maximum common - mode voltage slew rate that can be sustained while maintaining the voltage output (v o ) > 0.8 v ddx . |cm l | is the maximum common - mode voltage slew rate that can be sustained while maintaining v o > 0.8 v. the common - mode voltage slew rates apply to both rising and falling common - mode voltage edges. table 6 . total supply current vs. data throughput 1 mbps 25 mbps 100 mbps parameter symbol min typ max min typ max min typ max unit supply current adum 2 50n supply current side 1 i dd1 9.25 14.2 10.2 16.4 1 4.0 22.0 ma supply current side 2 i dd2 3.35 5.35 4.58 7.78 8.61 16.5 ma adum 2 51n supply current side 1 i dd1 8.14 13.4 9.14 15.4 13.1 21.4 ma supply current side 2 i dd2 4.98 8.65 6.14 10.8 10.1 17.8 ma adum 2 52n supply current side 1 i dd1 6.74 11.2 7.80 13.2 11.8 18.5 ma supply current side 2 i dd2 6.48 10.2 7.56 12.0 11.5 18.7 ma
data sheet adum250n/adum251n/adum252n rev. 0 | page 9 of 22 electrical character istics 1.8 v operation all typical specifications are at t a = 25c, v dd1 = v dd2 = 1.8 v. minimum/maximum specifications apply over the entire recommended operation range: 1.7 v v dd1 1.9 v, 1.7 v v dd2 1.9 v, and ? 40c t a + 125c , unless otherwise noted. switching specifications are tested with c l = 15 pf and cmos signal levels, unless otherwise noted. supply currents are specified with 50% duty cycle signals. table 7 . parameter symbol min typ max unit test conditions/comments switching specifications pulse width pw 6.6 ns within pwd limit data rate 1 150 mbps within pwd limit propagation delay t phl , t plh 5.8 8.7 15 ns 50% input to 50% output pulse width distortion pwd 0.7 5.0 ns |t plh ? t phl | change vs. temperature 1.5 ps/c propagation delay skew t psk 7.0 ns between any two units at the same temperature, voltage, and load channel matching codirectional t pskcd 0.7 5.0 ns opposing direction t pskod 0.7 5 .0 ns jitter 470 ps p -p see the jitter measurement section 70 ps rms see the jitter measurement section dc specifications input threshold voltage logic high v ih 0.7 v ddx v logic low v il 0.3 v ddx v output voltage logic high v oh v ddx ? 0.1 v ddx v i ox 2 = ?20 a, v ix = v ixh 3 v ddx ? 0.4 v ddx ? 0.2 v i ox 2 = ?2 ma, v ix = v ixh 3 logic low v ol 0.0 0.1 v i ox 2 = 20 a, v ix = v ixl 4 0.2 0.4 v i ox 2 = 2 ma, v ix = v ixl 4 input current per channel i i ?10 +0.01 +10 a 0 v v ix v ddx quiescent supply current adum 2 50n i dd1 (q) 2. 19 3. 35 ma v i 5 = 0 (n0), 1 (n1) 6 i dd2 (q) 3. 07 4. 29 ma v i 5 = 0 (n0), 1 (n1) 6 i dd1 (q) 1 6. 3 27. 0 ma v i 5 = 1 (n0), 0 (n1) 6 i dd2 (q) 3. 28 4. 61 ma v i 5 = 1 (n0), 0 (n1) 6 adum 2 51n i dd1 (q) 2 .44 3. 74 ma v i 5 = 0 (n0), 1 (n1) 6 i dd2 (q) 2. 91 3. 93 ma v i 5 = 0 (n0), 1 (n1) 6 i dd1 (q) 13.7 22. 5 ma v i 5 = 1 (n0), 0 (n1) 6 i dd2 (q) 6. 75 10. 7 ma v i 5 = 1 (n0), 0 (n1) 6 adum 2 52n i dd1 (q) 2. 58 3. 78 ma v i 5 = 0 (n0), 1 (n1) 6 i dd2 (q) 2. 64 3. 8 4 ma v i 5 = 0 (n0), 1 (n1) 6 i dd1 (q) 10. 7 19. 1 ma v i 5 = 1 (n0), 0 (n1) 6 i dd2 (q) 10. 1 16. 3 ma v i 5 = 1 (n0), 0 (n1) 6 dynamic supply current inputs switching, 50% duty cycle dynamic input i ddi (d) 0.01 ma/mbps dynamic output i ddo (d) 0.01 ma/mbps undervoltage lockout uvlo positive v ddx threshold v ddxuv+ 1.6 v negative v ddx threshold v ddxuv? 1.5 v v ddx hysteresis v ddxuvh 0.1 v
adum250n/a dum251n/adum252n data sheet rev. 0 | page 10 of 22 parameter symbol min typ max unit test conditions/comments ac specifications output rise/fall time t r /t f 2.5 ns 10% to 90% common - mode transient immunity 7 |cm h | 75 100 kv/s v ix = v ddx , v cm = 1000 v, transient magnitude = 800 v |cm l | 75 100 kv/s v ix = 0 v, v cm = 1000 v, transient magnitude = 800 v 1 150 mbps is the highest data rate that can be guaranteed, although hi gher data rates are possible. 2 i ox is t he channel x o utput current , where x = a, b, c, d , or e . 3 v ixh is the input side logic high. 4 v ixl is the input side logic low. 5 v i is the voltage input. 6 n 0 refers to the adum 2 50n0 / adum 2 51n0 / adum 2 52n0 models. n 1 refers to the adum 2 50n1 / adum 2 51n1 / adum 2 52n1 models . see the ordering guide section. 7 |cm h | is the maximum common - mode voltage slew rate that can be sustained while maintaining the voltage output (v o ) > 0.8 v ddx . |cm l | is the maximum common - mode voltage slew rate that can be sustained while maintaining v o > 0.8 v . the common - mode voltage slew rates apply to both rising and falling common - mode voltage edges. table 8 . total supply current vs. data throughput 1 mbps 25 mbps 100 mbps parameter symbol min typ max min typ max min typ max unit supply current adum 2 50n supply current side 1 i dd1 9. 07 14. 0 10. 0 16. 2 13.8 21.8 ma supply current side 2 i dd2 3. 30 5.3 0 4.5 5 7. 75 8. 71 16. 4 ma adum 2 51n supply current side 1 i dd1 7 . 99 13. 3 8 . 98 15. 3 12.8 21. 1 ma supply current side 2 i dd2 4. 89 8. 56 6. 06 10. 7 10.1 17.8 ma adum 2 52n supply current side 1 i dd1 6. 62 11. 1 7. 68 13. 1 11. 6 18. 3 ma supply current side 2 i dd2 6. 38 10. 1 7. 45 1 1 . 9 11.5 18.7 ma
data sheet adum250n/adum251n/adum252n rev. 0 | page 11 of 22 insulation and safet y related specificat ions for additional information, see http://www.analog.com/icouplersafety . table 9 . parameter symbol valu e unit test conditions/comments rated dielectric insulation voltage 5 000 v rms 1 - minute duration minimum external air gap (clearance) l (i01) 8.3 mm min measured from input terminals to output terminals, shortest distance through air minimum external tracking (creepage) l (i02) 8.3 mm min measured from input terminals to output terminals, shortest distance path along body minimum clearance in the plane of the printed circuit board (pcb clearance) l (pcb) 8.3 mm min measured from input terminals to output terminals, shortest distance through air, line of sight, in the pcb mounting plane minimum internal gap (internal clearance) 25.5 m min minimum distance through insulation tracking resistance (comparative tracking index) cti >400 v din iec 112/vde 0303 part 1 material group ii material group (din vde 0110, 1/89, table 1) package characterist ics table 10. parameter symbol min typ max unit test conditions/comments resistance (input to output) 1 r i- o 10 13 capacitance (input to output) 1 c i - o 2.2 pf f = 1 mhz input capacitance 2 c i 4.0 pf ic junction to ambient thermal resistance ja 4 5 c/w thermocouple located at center of package underside 1 the device is considered a 2 - terminal device: pin 1 through pin 8 are shorted together, and pin 9 through pin 16 are shorted together. 2 input capacitance is from any input data pin to ground. regulatory informati on see table 15 and the insulation lifetime section for details regarding recommended maximum working voltages for specific cross - isolation waveforms and insulation levels. table 11. ul (pending) csa (pending) vde (pending) cqc (pending) recognized under ul 1577 component recognition program 1 approved under csa component acceptance notice 5a certified according to din v vde v 0884 - 10 (vde v 0884 - 10):2006 -12 2 certified under cqc11 - 471543 - 2012, gb4943.1 - 2011: single protection, 5 000 v rms isolation voltage csa 60950 -1 - 07+a1+a2 and iec 60950 - 1, second edition, +a1+a2: reinforced insulation, v iorm = 849 v peak, v iosm = 10 k v peak basic insulation at 830 v rms (1 174 v peak) basic insulation at 83 0 v rms ( 1174 v peak) basic insulation, v iorm = 849 v peak, v iosm = 1 6 kv peak reinforced insulation at 415 v rms (5 87 v peak) reinforced insulation at 415 v rms ( 587 v peak) tropical climate, altitude 5000 meters iec 60601 - 1 edition 3+a 1 , two means of patient protection ( 2 mopp ), 261 v rms ( 369 v peak) csa 61010 - 1 - 12 and iec 61010 - 1 third edition: basic insulation at 300 v rms mains, 830 v rms secondary ( 1174 v peak) file e214100 file 205078 file 2471900 - 4880 - 0001 file (pending) 1 in accordance with ul 1577, each adum 2 50n / adum 2 51n / adum 2 52n in the ri - 16 wide - body (soic_ic) package is proof tested by applying an insulation test voltage 60 00 v rms for 1 sec. 2 in accordance with din v vde v 0884 - 10, each adum 2 50n / adum 2 51n / adum 2 52n in the ri - 16 wi de - body (soic_ic) package is proof tested by applying an insulation test voltage 1 592 v peak for 1 sec (partial discharge detection limit = 5 pc). the * marking branded on the component designates din v vde v 08 84- 10 approval.
adum250n/a dum251n/adum252n data sheet rev. 0 | page 12 of 22 din v vde v 0884 - 10 (vde v 0884 - 10) insulation character istics these isolators are suitable for reinforced electrical isolation only within the safety limit data. protective circuits ensur e the maintenance of the safety data. the * marking on packages denotes din v vde v 0884 - 10 approval. table 12. description test conditions/comments symbol characteristic unit installation classification per din vde 0110 for rated mains voltage 150 v rms i to iv for rated mains voltage 300 v rms i to iv for rated mains voltage 600 v rms i to iii climatic classification 40/125/21 pollution degree per din vde 0110, table 1 2 maximum working insulation voltage v iorm 849 v peak input to output test voltage, method b1 v iorm 1.875 = v pd (m) , 100% production test, t ini = t m = 1 sec, partial discharge < 5 pc v pd (m) 1 592 v peak input to output test voltage, method a v pd (m) after environmental tests subgroup 1 v iorm 1.5 = v pd (m) , t ini = 60 sec, t m = 10 sec, partial discharge < 5 pc 1274 v peak after input and/or safety test subgroup 2 and subgroup 3 v iorm 1.2 = v pd (m) , t ini = 60 sec, t m = 10 sec, partial discharge < 5 pc 1019 v peak highest allowable overvoltage v iotm 8 0 00 v peak surge isolation voltage basic v peak = 10 kv, 1.2 s rise time, 50 s, 50% fall time v iosm 1 6 , 000 v peak surge isolation voltage reinforced v peak = 10 kv, 1.2 s rise time, 50 s, 50% fall time v iosm 10, 000 v peak safety limiting values maximum value allowed in the event of a failure (see figure 4 ) maximum junction temperature t s 150 c total power dissipation at 25c p s 2.78 w insulation resistance at t s r s >10 9 figure 4. thermal derating curve, dependence of safety limiting values with ambient temperature per din v vde v 0884 - 10 recommended operatin g conditions table 13. parameter symbol rating operating temperature range t a ?40c to +125c supply voltages range v dd1 , v dd2 1.7 v to 5.5 v input signal rise and fall times 1.0 ms 3.0 2.5 2.0 1.5 0.5 1.0 0 0 200 150 100 50 safe limiting power (w) ambient temperature (c) 14997-004
data sheet adum250n/adum251n/adum252n rev. 0 | page 13 of 22 absolute maximum ratings t a = 25c, unless otherwise noted. table 14. parameter rating storage temperature (t st ) range ?65c to +150c ambient operating temperature (t a ) range ?40c to +125c supply voltages (v dd1 , v dd2 ) ?0.5 v to +7.0 v input voltages (v ia , v ib , v ic , v id , v ie ) ?0.5 v to v ddi 1 + 0.5 v output voltages (v oa , v ob , v oc , v od , v oe ) ?0.5 v to v ddo 2 + 0.5 v average output current per pin 3 side 1 output current (i o1 ) ?10 ma to +10 ma side 2 output current (i o2 ) ?10 ma to +10 ma common-mode transients 4 ?150 kv/s to +150 kv/s 1 v ddi is the input side supply voltage. 2 v ddo is the output side supply voltage. 3 see figure 4 for the maximum rated current values for various temperatures. 4 refers to the common-mode transients across the insulation barrier. common-mode transients exceeding the absolute maximum ratings may cause latch-up or permanent damage. stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. esd caution table 15. maximum continuous working voltage 1 parameter rating constraint ac voltage bipolar waveform basic insulation 849 v peak 50-year minimum insulation lifetime reinforced insulation 819 v peak lifetime limited by pack age creepage maximum approved working voltage per iec 60950-1 unipolar waveform basic insulation 1698 v peak 50-year minimum insulation lifetime reinforced insulation 943 v peak lifetime limited by pack age creepage maximum approved working voltage per iec 60950-1 dc voltage basic insulation 1157 v peak lifetime limited by package creepage maximum approved working voltage per iec 60950-1 reinforced insulation 579 v peak lifetime limited by pack age creepage maximum approved working voltage per iec 60950-1 1 refers to the continuous voltage magnitude imposed across the isolation barrier. see the insulation lifetime section for more details. truth table table 16. adum250n / adum251n / adum252n truth table (positive logic) v ix input 1, 2 v ddi state 2 v ddo state 2 default low (n0), v ox output 1, 2, 3 default high (n1), v ox output 1, 2, 3 test conditions/comments l powered powered l l normal operation h powered powered h h normal operation l unpowered powered l h fail-safe output x 4 powered unpowered indeterminate indeterminate output unpowered 1 l means low, h means high, and x means dont care. 2 v ix and v ox refer to the input and output signals of a given channel (a, b, c, d, or e). v ddi and v ddo refer to the supply voltages on the input and output sides of the given channel, respectively. 3 n0 refers to the adum250n0 / adum251n0 / adum252n0 models, n1 refers to the adum250n1 / adum251n1 / adum252n1 models. see the ordering guide section. 4 input pins (v ix ) on the same side as an unpowered supply must be in a low state to avoid powering the device through its esd protection circui try.
adum250n/adum251n/adum252n data sheet rev. 0 | page 14 of 22 pin configurations and function descriptions figure 5. adum250n pin configuration table 17. adum250n pin function descriptions pin no. 1 mnemonic description 1 v dd1 supply voltage for isolator side 1. 2 v ia logic input a. 3 v ib logic input b. 4 v ic logic input c. 5 v id logic input d. 6 v ie logic input e. 7 nic no internal connection. leave this pin floating. 8 gnd 1 ground 1. ground reference for isolator side 1. 9 gnd 2 ground 2. ground reference for isolator side 2. 10 nic no internal connection. leave this pin floating. 11 v oe logic output e. 12 v od logic output d. 13 v oc logic output c. 14 v ob logic output b. 15 v oa logic output a. 16 v dd2 supply voltage for isolator side 2. 1 reference the an-1109 application note for specific layout guidelines. v dd1 v ia v ib v ic v id v ie nic v oa v ob v oc v od v oe nic gnd 1 v dd2 gnd 2 1 2 3 4 16 15 14 13 5 12 6 11 7 10 8 9 adum250n top view (not to scale) notes 1. nic = no internal connection. 14997-005
data sheet adum250n/adum251n/adum252n rev. 0 | page 15 of 22 figure 6. adum251n pin configuration table 18. adum251n pin function descriptions pin no. 1 mnemonic description 1 v dd1 supply voltage for isolator side 1. 2 v ia logic input a. 3 v ib logic input b. 4 v ic logic input c. 5 v id logic input d. 6 v oe logic output e. 7 nic no internal connection. leave this pin floating. 8 gnd 1 ground 1. ground reference for isolator side 1. 9 gnd 2 ground 2. ground reference for isolator side 2. 10 nic no internal connection. leave this pin floating. 11 v ie logic input e. 12 v od logic output d. 13 v oc logic output c. 14 v ob logic output b. 15 v oa logic output a. 16 v dd2 supply voltage for isolator side 2. 1 reference the an-1109 application note for specific layout guidelines. v dd1 v ia v ib v ic v id v oe nic v oa v ob v oc v od v ie nic gnd 1 v dd2 gnd 2 1 2 3 4 16 15 14 13 5 12 6 11 7 10 8 9 adum251n top view (not to scale) n otes 1 . nic = no internal connection. 14997-006
adum250n/adum251n/adum252n data sheet rev. 0 | page 16 of 22 figure 7. adum252n pin configuration table 19. adum252n pin function descriptions pin no. 1 mnemonic description 1 v dd1 supply voltage for isolator side 1. 2 v ia logic input a. 3 v ib logic input b. 4 v ic logic input c. 5 v od logic output d. 6 v oe logic output e. 7 nic no internal connection. leave this pin floating. 8 gnd 1 ground 1. ground reference for isolator side 1. 9 gnd 2 ground 2. ground reference for isolator side 2. 10 nic no internal connection. leave this pin floating. 11 v ie logic input e. 12 v id logic input d. 13 v oc logic output c. 14 v ob logic output b. 15 v oa logic output a. 16 v dd2 supply voltage for isolator side 2. 1 reference the an-1109 application note for specific layout guidelines. v dd1 v ia v ib v ic v od v oe nic v oa v ob v oc v id v ie nic gnd 1 v dd2 gnd 2 1 2 3 4 16 15 14 13 5 12 6 11 7 10 8 9 adum252n top view (not to scale) notes 1. nic = no internal connection. 14997-007
data sheet adum250n/adum251n/adum252n rev. 0 | page 17 of 22 typical performance characteristics figure 8. adum250n i dd1 supply current vs. data rate at various voltages figure 9. adum250n i dd2 supply current vs. data rate at various voltages figure 10. adum251n i dd1 supply current vs. data rate at various voltages figure 11. adum251n i dd2 supply current vs. data rate at various voltages figure 12. adum252n i dd1 supply current vs. data rate at various voltages figure 13. adum252n i dd2 supply current vs. data rate at various voltages 25 20 15 10 5 0 0 20 40 60 80 100 120 140 160 i dd1 supply current (ma) data rate (mbps) 5v 3.3v 2.5v 1.8v 14997-008 25 20 15 10 5 0 0 20 40 60 80 100 120 140 160 i dd2 supply current (ma) data rate (mbps) 5v 3.3v 2.5v 1.8v 14997-009 25 20 15 10 5 0 0 20 40 60 80 100 120 140 160 i dd1 supply current (ma) data rate (mbps) 5v 3.3v 2.5v 1.8v 14997-010 25 20 15 10 5 0 0 20 40 60 80 100 120 140 160 i dd2 supply current (ma) data rate (mbps) 5v 3.3v 2.5v 1.8v 14997-011 25 20 15 10 5 0 0 20 40 60 80 100 120 140 160 i dd1 supply current (ma) data rate (mbps) 5v 3.3v 2.5v 1.8v 14997-012 25 20 15 10 5 0 0 20 40 60 80 100 120 140 160 i dd2 supply current (ma) data rate (mbps) 5v 3.3v 2.5v 1.8v 14997-013
adum250n/adum251n/adum252n data sheet rev. 0 | page 18 of 22 figure 14. propagation delay, t plh vs. temperature at various voltages figure 15. propagation delay, t phl vs. temperature at various voltages 14 12 10 8 6 4 2 0 ?40 ?20 0 20 40 60 80 120100 140 propagation delay, t plh (ns) temperature (c) 5v 3.3v 2.5v 1.8v 14997-014 14 12 10 8 6 4 2 0 ?40 ?20 0 20 40 60 80 120100 140 propagation delay, t phl (ns) temperature (c) 5v 3.3v 2.5v 1.8v 14997-015
data sheet adum250n/adum251n/adum252n rev. 0 | page 19 of 22 theory of operation the adum250n / adum251n / adum252n use a high frequency carrier to transmit data across the isolation barrier using i coupler chip scale transformer coils separated by layers of polyimide isolation. using an on/off keying (ook) technique and the differential architecture shown in figure 16 and figure 17, the adum250n / adum251n / adum252n have very low propagation delay and high speed. internal regulators and input/output design techniques allow logic and supply voltages over a wide range from 1.7 v to 5.5 v, offering voltage translation of 1.8 v, 2.5 v, 3.3 v, and 5 v logic. the architecture is designed for high common-mode transient immunity and high immunity to electrical noise and magnetic interference. radiated emissions are minimized with a spread spectrum ook carrier and other techniques. figure 16 shows the waveforms for models of the adum250n0/ adum251n0/ adum252n0 that have the condition of the fail- safe output state equal to low, where the carrier waveform is off when the input state is low. if the input side is off or not operating, the fail-safe output state of low sets the output to low. for the adum250n1 / adum251n1 / adum252n1 that have a fail-safe output state of high, figure 17 illustrates the conditions where the carrier waveform is off when the input state is high. when the input side is off or not operating, the fail-safe output state of high sets the output to high. see the ordering guide for the model numbers that have the fail-safe output state of low or the fail-safe output state of high. figure 16. operational block diagram of a single channel with a low fail-safe output state figure 17. operational block diagram of a single channel with a high fail-safe output state transmitter gnd 1 gnd 2 v in v out receiver regulator regulator 14997-016 transmitter gnd 1 gnd 2 v in v out receiver regulator regulator 14997-017
adum250n/adum251n/adum252n data sheet rev. 0 | page 20 of 22 applications information pcb layout the adum250n / adum251n / adum252n digital isolators require no external interface circuitry for the logic interfaces. power supply bypassing is strongly recommended at the input and output supply pins (see figure 18). bypass capacitors are connected between pin 1 and pin 8 for v dd1 and between pin 9 and pin 16 for v dd2 . the recommended bypass capacitor value is between 0.01 f and 0.1 f. the total lead length between both ends of the capacitor and the input power supply pin must not exceed 10 mm. figure 18. recommended printed circuit board layout in applications involving high common-mode transients, ensure that board coupling across the isolation barrier is minimized. furthermore, design the board layout such that any coupling that does occur equally affects all pins on a given component side. failure to ensure this can cause voltage differentials between pins exceeding the absolute maximum ratings of the device, thereby leading to latch-up or permanent damage. see the an-1109 application note for board layout guidelines. propagation delay related parameters propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. the propagation delay to a logic 0 output may differ from the propagation delay to a logic 1 output. figure 19. propagation delay parameters pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the timing of the input signal is preserved. channel matching is the maximum amount the propagation delay differs between channels within a single adum250n / adum251n / adum252n component. propagation delay skew is the maximum amount the propagation delay differs between multiple adum250n / adum251n / adum252n components operating under the same conditions. jitter measurement figure 20 shows the eye diagram for the adum250n / adum251n / adum252n . the measurement was taken using an agilent 81110a pulse pattern generator at 150 mbps with pseudorandom bit sequences (prbs) 2(n ? 1), n = 14, for 5 v supplies. jitter was measured with the tektronix model 5104b oscilloscope, 1 ghz, 10 gsps with the dpojet jitter and eye dia- gram analysis tools. the result shows a typical measurement on the adum250n / adum251n / adum252n with 490 ps p-p jitter. figure 20. adum250n / adum251n / adum252n eye diagram insulation lifetime all insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. the rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation as well as on the materials and material interfaces. the two types of insulation degradation of primary interest are breakdown along surfaces exposed to the air and insulation wear out. surface breakdown is the phenomenon of surface tracking, and the primary determinant of surface creepage requirements in system level standards. insulation wear out is the phenomenon where charge injection or displacement currents inside the insulation material cause long-term insulation degradation. surface tracking surface tracking is addressed in electrical safety standards by setting a minimum surface creepage based on the working voltage, the environmental conditions, and the properties of the insulation material. safety agencies perform characterization testing on the surface insulation of components that allows the components to be categorized in different material groups. lower material group ratings are more resistant to surface tracking and, therefore, can provide adequate lifetime with smaller creepage. the minimum creepage for a given working voltage and material group is in each system level standard and is based on the total rms voltage across the isolation, pollution degree, and material group. the material group and creepage for the adum250n / adum251n / adum252n isolators are presented in table 9. v dd1 v ia v ib v ic v id , v od v ie , v oe nic gnd 1 v dd2 v oa v ob v oc v id , v od v ie , v oe nic gnd 2 14997-018 input (v ix ) output (v ox ) t plh t phl 50% 50% 14997-019 voltage (v) time (ns) 14997-020
data sheet adum250n/adum251n/adum252n rev. 0 | page 21 of 22 insulation wear out the lifetime of insulation caused by wear out is determined by its thickness, material properties, and the voltage stress applied. it is important to verify that the product lifetime is adequate at the application working voltage. the working voltage supported by an isolator for wear out may not be the same as the working voltage supported for tracking. the working voltage applicable to tracking is specified in most standards. testing and modeling have shown that the primary driver of long- term degradation is displacement current in the polyimide insulation causing incremental damage. the stress on the insulation can be broken down into broad categories, such as: dc stress, which causes very little wear out because there is no displacement current, and an ac component time varying voltage stress, which causes wear out. the ratings in certification documents are usually based on 60 hz sinusoidal stress because this reflects isolation from line voltage. however, many practical applications have combinations of 60 hz ac and dc across the barrier as shown in equation 1. because only the ac portion of the stress causes wear out, the equation can be rearranged to solve for the ac rms voltage, as is shown in equation 2. for insulation wear out with the polyimide materials used in these products, the ac rms voltage determines the product lifetime. 22 dc rmsac rms vvv ? ? (1) or 2 2 dc rms rmsac vv v ?? (2) where: v rms is the total rms working voltage. v ac rms is the time varying portion of the working voltage. v dc is the dc offset of the working voltage. calculation and use of parameters example the following example frequently arises in power conversion applications. assume that the line voltage on one side of the isolation is 240 v ac rms and a 400 v dc bus voltage is present on the other side of the isolation barrier. the isolator material is polyimide. to establish the critical voltages in determining the creepage, clearance, and lifetime of a device, see figure 21 and the following equations. figure 21. critical voltage example the working voltage across the barrier from equation 1 is 22 dc rmsac rms vvv ? ? 22 400240 ?? rms v v rms = 466 v this v rms value is the working voltage used together with the material group and pollution degree when looking up the creepage required by a system standard. to determine if the lifetime is adequate, obtain the time varying portion of the working voltage. to obtain the ac rms voltage, use equation 2. 2 2 dc rms rmsac vv v ?? 22 400466 ?? rmsac v v ac rms = 240 v rms in this case, the ac rms voltage is simply the line voltage of 240 v rms. this calculation is more relevant when the waveform is not sinusoidal. the value is compared to the limits for working voltage in table 15 for the expected lifetime, less than a 60 hz sine wave, and it is well within the limit for a 50-year service life. note that the dc working voltage limit in table 15 is set by the creepage of the package as specified in iec 60664-1. this value can differ for specific system level standards. isolation voltage time v ac rms v rms v dc 14997-021 v peak
adum250n/adum251n/adum252n data sheet rev. 0 | page 22 of 22 outline dimensions figure 22. 16-lead standard small outline package, with increased creepage [soic_ic] wide body (ri-16-2) dimensions shown in millimeters ordering guide model 1 temperature range no. of inputs, v dd1 side no. of inputs, v dd2 side withstand voltage rating (kv rms) fail-safe output state package description package option ADUM250N1BRIZ ?40c to +125c 5 0 5.0 high 16-lead soic_ic ri-16-2 ADUM250N1BRIZ-rl ?40c to +125c 5 0 5.0 high 16-lead soic_ic ri-16-2 adum250n0briz ?40c to +125c 5 0 5.0 low 16-lead soic_ic ri-16-2 adum250n0briz-rl ?40c to +125c 5 0 5.0 low 16-lead soic_ic ri-16-2 adum251n1briz ?40c to +125c 4 1 5.0 high 16-lead soic_ic ri-16-2 adum251n1briz-rl ?40c to +125c 4 1 5.0 high 16-lead soic_ic ri-16-2 adum251n0briz ?40c to +125c 4 1 5.0 low 16-lead soic_ic ri-16-2 adum251n0briz-rl ?40c to +125c 4 1 5.0 low 16-lead soic_ic ri-16-2 adum252n1briz ?40c to +125c 3 2 5.0 high 16-lead soic_ic ri-16-2 adum252n1briz-rl ?40c to +125c 3 2 5.0 high 16-lead soic_ic ri-16-2 adum252n0briz ?40c to +125c 3 2 5.0 low 16-lead soic_ic ri-16-2 adum252n0briz-rl ?40c to +125c 3 2 5.0 low 16-lead soic_ic ri-16-2 1 z = rohs compliant part. 11-15-2011-a 16 9 8 1 seating plane coplanarity 0.1 1.27 bsc 12.85 12.75 12.65 7.60 7.50 7.40 2.64 2.54 2.44 1.01 0.76 0.51 0.30 0.20 0.10 10.51 10.31 10.11 0.46 0.36 2.44 2.24 pin 1 mark 1.93 ref 8 0 0.32 0.23 0.71 0.50 0.31 45 0.25 bsc gage plane compliant to jedec standards ms-013-ac ?2016 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d14997-0-12/16(0)

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